Nvidia GB10's Memory Subsystem, from the CPU Side

1 comments

• Neywiny 2 hours ago
  I don't understand on one of the later graphs the core to core latency for strix halo goes out to 32 cores but he says only has 16 cores?
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  • wtallis 2 hours ago
    AMD's cores have SMT, allowing them to run two threads at a time and appear to the OS and its scheduler as two logical cores despite being implemented as a single physical core.
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    • Neywiny 1 hour ago
      What pattern in the data shows that's what's being measured? I would expect to see basically 0 latency between adjacent "cores" then since L1 is shared per thread?
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      • monocasa 38 minutes ago
        Co resident threads might not get any speed up here since coherency instructions are functionally operations on the L2 cache.